Rapicorn - Experimental UI Toolkit - Source Code
13.07.0
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00001 // Licensed GNU LGPL v3 or later: http://www.gnu.org/licenses/lgpl.html 00002 #ifndef __RAPICORN_CPUASM_HH__ 00003 #define __RAPICORN_CPUASM_HH__ 00004 00005 #include <rcore/cxxaux.hh> 00006 00007 // == Memory Fences/Barriers == 00008 #define RAPICORN_CACHE_LINE_ALIGNMENT 128 00009 #if defined __x86_64__ || defined __amd64__ 00010 #define RAPICORN_MFENCE __sync_synchronize() 00011 #define RAPICORN_SFENCE __asm__ __volatile__ ("sfence" ::: "memory") 00012 #define RAPICORN_LFENCE __asm__ __volatile__ ("lfence" ::: "memory") 00013 #else // !x86/64 00014 #define RAPICORN_MFENCE __sync_synchronize() ///< Memory Fence - prevent processor (and compiler) from reordering loads/stores (read/write barrier). 00015 #define RAPICORN_SFENCE __sync_synchronize() ///< Store Fence - prevent processor (and compiler) from reordering stores (write barrier). 00016 #define RAPICORN_LFENCE __sync_synchronize() ///< Load Fence - prevent processor (and compiler) from reordering loads (read barrier). 00017 #endif 00018 #define RAPICORN_CFENCE __asm__ __volatile__ ("" ::: "memory") ///< Compiler Fence, prevent compiler from reordering non-volatile loads/stores. 00019 00020 // == RDTSC == 00021 #if defined __i386__ || defined __x86_64__ || defined __amd64__ 00022 #define RAPICORN_HAVE_X86_RDTSC 1 00023 #define RAPICORN_X86_RDTSC() ({ Rapicorn::uint32 __l_, __h_, __s_; \ 00024 __asm__ __volatile__ ("rdtsc" : "=a" (__l_), "=d" (__h_)); \ 00025 __s_ = __l_ + (Rapicorn::uint64 (__h_) << 32); __s_; }) 00026 #else 00027 #define RAPICORN_HAVE_X86_RDTSC 0 00028 #define RAPICORN_X86_RDTSC() (0) 00029 #endif 00030 00031 #endif // __RAPICORN_CPUASM_HH__